Semiconductor storage device

A semiconductor storage device comprising:

• a first plane and a second plane each including a memory cell array that includes a plurality of memory cells;
• a third plane and a fourth plane each including a memory cell array that includes a plurality of memory cells;
• an input/output circuit configured to receive data to be written in the memory cells from a controller;
• and
• a control circuit configured to perform a write operation on the first and second planes synchronously in response to first and second commands and a write operation on the first and second planes synchronously in response to third and fourth commands, wherein
• the first plane further includes a first sense amplifier circuit electrically connected a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit,
• the second plane further includes a second sense amplifier circuit electrically connected a second memory cell of the second plane and a second latch circuit connected in series between the input/output circuit and the second sense amplifier circuit, and
• the control circuit is configured to carry out the write operation on the first memory cell and the second memory cell synchronously using the first latch circuit and the second latch circuit, respectively, and while carrying out the write operation, accept the third command before use of the first latch circuit and the second latch circuit during the write operation has ended.