Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage

A non-volatile memory device comprising:

• a plurality of non-volatile memory cell transistors;
• a plurality of main word lines, each main word line of the plurality of main word lines coupled to a corresponding group of local word lines, each local word line coupled to gate terminals of its corresponding non-volatile memory cell transistors of the plurality of non-volatile memory cell transistors;
• a voltage circuit configured to provide a positive well bias voltage, a negative word line voltage, and a positive word line voltage, the voltage circuit coupled to a p-well to apply the positive well bias voltage to the plurality of non-volatile memory cell transistors for an erase operation;
• and
• driver circuit configured to:
• pass the negative word line voltage on a selected main word line of the plurality of main word lines to its corresponding group of selected local word lines for the erase operation, the corresponding group of selected local word lines being coupled to gate terminals of corresponding group of selected non-volatile memory cell transistors to be erased, the difference between the positive well bias voltage and the negative word line voltage being sufficient to erase non-volatile memory cell transistors;
• and
• pass the positive word line voltage on unselected main word lines of the plurality of main word lines to their corresponding groups of unselected local word lines, the corresponding group of unselected local word lines being coupled to gate terminals of corresponding groups of unselected non-volatile memory cell transistors, the difference between the positive well bias voltage and the positive word line voltage being insufficient to erase non-volatile memory cell transistors.