Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory strings each including a select transistor and a memory cell that is connected to one end of the select transistor and can be set to any one of at least four different threshold voltages;
• a select gate line that is commonly connected to gates of the select transistors of the plurality of memory strings;
• a plurality of bit lines that are individually connected to other ends of the select transistors of the plurality of memory strings;
• a word line that is commonly connected to gates of the memory cells of the plurality of memory strings;
• and
• a control unit configured to execute a write sequence to write predetermined data into the memory cells, the write sequence including a plurality of loops, each loop including a program operation to write data into the respective memory cells and a verify operation to verify the data written in the respective memory cells,
• wherein a voltage applied to the select gate line in the program operation of a last loop of the plurality of loops is lower than a voltage applied to the select gate line in the program operation of a first loop of the plurality of loops.