US 2020/0090753 A1 · SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM

Abstract

A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.

A memory system comprising:

a semiconductor storage device;
and
a controller,
the semiconductor storage device including:
a first memory string having first, second, and third memory cells, and a first select transistor;
a second memory string having fourth, fifth, and sixth memory cells, and a second select transistor;
a third memory string having seventh, eighth, and ninth memory cells, and a third select transistor;
a first word line that is connected to gates of the first, fourth, and seventh memory cells;
a second word line that is connected to gates of the second, fifth, and eighth memory cells;
a third word line that is connected to gates of the third, sixth, and ninth memory cells;
first, second, and third select gate lines that are respectively connected to the first, second, and third select transistors;
and
a row decoder that is connected to the first, second, and third word lines and the first, second, and third select gate lines,
wherein a write operation for writing n-bit data in the first to ninth memory cells, where n is an integer greater than or equal to two, includes a first write operation and a second write operation, the first to ninth memory cells having first to ninth addresses, respectively, and
wherein, during the write operation, the controller sends, to the semiconductor storage device,
a first command set which instructs the first write operation and assigns the first address,
after the first command set is sent, a second command set which instructs the first write operation and assigns the fourth address of the fourth memory cell,
after the second command set is sent, a third command set which instructs the first write operation and assigns the seventh address,
after the third command set is sent, a fourth command set which instructs the first write operation and assigns the second address,
after the fourth command set is sent, a fifth command set which instructs the second write operation and assigns the first address,
after the fifth command set is sent, a sixth command set which instructs the first write operation and assigns the fifth address,
after the sixth command set is sent, a seventh command set which instructs the second write operation and assigns the fourth address,
after the seventh command set is sent, an eighth command set which instructs the first write operation and assigns the eighth address,
after the eighth command set is sent, a ninth command set which instructs the second write operation and assigns the seventh address,
after the ninth command set is sent, a tenth command set which instructs the first write operation and assigns the sixth address,
after the tenth command set is sent, an eleventh command set which instructs the second write operation and assigns the fifth address,
after the eleventh command set is sent, a twelfth command set which instructs the first write operation and assigns the ninth address,
after the twelfth command set is sent, a thirteenth command set which instructs the second write operation and assigns the eighth address,
after the thirteenth command set is sent, a fourteenth command set which instructs the first write operation and assigns the third address, and
after the fourteenth command set is sent, a fifteenth command set which instructs the second write operation and assigns the second address.

27 more elements

Semiconductor storage device and memory system

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Semiconductor storage device and memory system

Life of this patent

Abstract

Claims19