Semiconductor memory device applying different voltages to respective select gate lines

A semiconductor memory device comprising:

• a memory string including first and second select transistors and memory cell transistors which are serially connected in this order;
• a bit line connected to the first select transistor;
• word lines which are connected to gates of the memory cell transistors, respectively, and which are stacked via insulating layers;
• first and second select gate lines which are connected to gates of the first and second select transistors, respectively, and which are stacked on the word lines via insulating layers;
• a first contact plug connected to the first select gate line;
• a second contact plug connected to the second select gate line;
• a first wiring layer provided on the first and second contact plugs;
• and
• a row decoder connected to the first wiring layer,
• wherein the row decoder applies the same voltage to the first and second select gate lines, and
• the first and second select gate lines are electrically isolated from one another at a second end opposite, across the memory string, to a first end on a side where the row decoder is disposed.