Row hammer refresh for content addressable memory devices
AssigneeMicron Technology, Inc.
InventorsYu Zhang, Jun Wu, Yuan He
Life of this patent
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Abstract
A method of operating a memory device may include receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM). The method may further include storing, during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Moreover, the method may include refreshing each stored RHA of the CAM via a RHR during the RHR interval. Semiconductor devices and an electronic system are also described.
Claims20
A method of operating a memory device, comprising:
- receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM);
- storing, during each phase of the RHR interval and in response to a randomly generated trigger signal during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register;
- and
- refreshing each stored RHA of the CAM via a RHR during the RHR interval.
(canceled)
A semiconductor device, comprising:
- a content addressable memory (CAM) array including row addresses;
- and
- a control circuit including registers and configured to select an active phase of a row hammer refresh (RHR) interval based on a received phase control signal, the control circuit further configured to, for each phase of the RHR interval:
- receive at least one address of the row addresses;
- and
- store, in an active register, one received address of the at least one received address as a row hammer address (RHA), the active register associated with the active phase;
- the control circuit further configured to transmit an RHR signal to the CAM array to refresh each stored RHA address during the RHR interval.
An electronic system, comprising:
- at least one input device;
- at least one output device;
- at least one processor device operably coupled to the input device and the output device;
- and
- at least one semiconductor device operably coupled to the at least one processor device and comprising:
- a content addressable memory (CAM) array:
- and
- a control circuit coupled to the CAM array and configured to:
- store a first row hammer address (RHA) in a first register during a first phase of a row hammer refresh (RHR) interval;
- store a second RHA in a second register during a second phase of the RHR interval;
- store a third RHA in a third register during a third phase of the RHR interval;
- store a fourth RHA in a fourth register during a fourth phase of the RHR interval;
- and
- transmit an RHR signal to the CAM array to refresh each of the first RHA, the second RHA, the third RHA, and the fourth RHA of the CAM array during the RHR interval.
Dependencies are inferred from the claim text.