US 2020/0090748 A1Published application

Random bit cell with memory units

AssigneeeMemory Technology Inc.

InventorsChien-Han Wu, Chun-Hung Lu, Chun-Hung Lin, Cheng-Da Huang

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Abstract

A random bit cell incudes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

Claims20

Dependent claims

A random bit cell comprising:

a volatile memory unit having a first data terminal and a second data terminal;
a first non-volatile memory unit coupled to the first data terminal of the volatile memory unit;
a second non-volatile memory unit coupled to the second data terminal of the volatile memory unit;
a first select transistor having a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line;
and
a second select transistor having a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to the word line;
wherein:
during an enroll operation, a programming state of one of the first non-volatile memory unit and the second non-volatile memory unit is changed;
and
during a load operation after the enroll operation, the volatile memory unit is configured to store a random bit according to programming states of the first non-volatile memory unit and the second non-volatile memory unit.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/513,740Filed 17 Jul 2019
Priority: 19 Sep 2018
Published: 19 Mar 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification25 codes

H10B 41/60
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: the control gate being a doped region, e.g. single-poly…
G11C 7/24
Arrangements for writing information into, or reading information out from, a digital store: memory cell safety or protection circuits, e.g.…
G11C 11/165
Using elements in which the storage effect is based on magnetic spin effect: auxiliary circuits
G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits