Memory device

A memory device comprising:

• a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines;
• a first decoder circuit configured to determine a selected bit line and unselected bit lines among the plurality of bit lines;
• a second decoder circuit configured to determine a selected word line and unselected word lines among the plurality of word lines;
• a sense amplifier including an input terminal connected to the selected word line;
• and
• a current compensation circuit including,
• a first transistor connected between a first power node and at least one of the unselected bit lines,
• a second transistor connected to the first power node, the second transistor controlled by a same control signal as the first transistor,
• a third transistor connected between the second transistor and a second power node, and
• a fourth transistor connected between the input terminal of the sense amplifier and the second power node, the fourth transistor configured to mirror a current of the third transistor.

A memory device comprising:

• a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines, the plurality of bit lines including a selected bit line and unselected bit lines excluding the selected bit line;
• a decoder circuit configured to precharge a selected word line among the plurality of word lines for a first time period, and to connect the selected word line to a current path for a second time period, subsequent to the first time period;
• a bleeding circuit configured to provide the current path drawing a leakage current from the selected word line for the second time period, the leakage current corresponding to off-current flowing in at least one of the unselected bit lines;
• and
• a sense amplifier configured to compare a sensing voltage detected through the selected word line with a reference voltage for a third time period, the third time period being subsequent to the second time period.