US 2020/0090744 A1Published application

Semiconductor storage device

AssigneeToshiba Memory Corporation

InventorHiroyuki HARA

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Abstract

A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.

Claims20

Dependent claims

A semiconductor storage device, comprising:

first, second, and third wiring layers, each including a plurality of first wirings extending in a first direction and arranged side by side in a second direction perpendicular to the first direction;
fourth and fifth wiring layers, each including a plurality of second wirings extending in the second direction and arranged side by side in the first direction, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers;
a memory cell array having a plurality of memory cells formed at intersections of the first and second wirings of adjacent wiring layers;
a first contact electrically connected to a first wiring of the first wiring layer, in a hook-up region;
a second contact electrically connected to a first wiring of the second wiring layer, in the hook-up region;
a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring;
a first drive circuit electrically connected to the first connection wiring;
and
a second drive circuit electrically connected to the second connection wiring.

6 more elements

A semiconductor storage device of a cross-point type, comprising:

a plurality of bit line and word line wiring layers that are alternately stacked in a first direction;
a memory cell array having a plurality of memory cells formed at intersections of the bit line and word line wirings of adjacent wiring layers;
a first contact electrically connected to a first bit line wiring in a hook-up region;
a second contact electrically connected to a second bit line wiring in the hook-up region;
a connection wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring;
a first drive circuit electrically connected to the first connection wiring;
and
a second drive circuit electrically connected to the second connection wiring, wherein
the plurality of bit line and word line wiring layers include first and second bit line wiring layers, and a word line wiring layer between the first and second bit line wiring layers, and
the first contact is electrically connected to a bit line wiring in the first bit line wiring layer and the second contact is electrically connected to a bit line wiring in the second bit line wiring layer.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/285,121Filed 25 Feb 2019
Priority: JP 2018-17478719 Sep 2018
Published: 19 Mar 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 13/0023
Auxiliary circuits: address circuits or decoders
G11C 13/003
Auxiliary circuits: cell access
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out