System and method for performing a concurrent multiple page read of a memory array

A memory device comprising:

• a memory array comprising a first plane and a second plane;
• and
• control circuitry comprising:
• first wordline control logic including first driver circuitry to apply a first voltage to a first wordline to access the first plane, and
• second wordline control logic including second driver circuitry to apply a second voltage to a second wordline to access the second plane concurrently with the application of the first voltage to the first wordline to access the first plane.

A system comprising:

• a processor;
• and
• memory coupled with the processor, the memory comprising:
• a memory array comprising a first plane and a second plane;
• and
• control circuitry comprising:
• first wordline control logic including first driver circuitry to apply a first voltage to a first wordline to access the first plane, and
• second wordline control logic including second driver circuitry to apply a second voltage to a second wordline to access the second plane concurrently with the application of the first voltage to the first wordline to access the first plane.