Memory system and method of controlling memory system

Abstract

A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n≥3). The first circuit is configured to calculate an estimated value of each of n−m determination voltages based on values of m determination voltages (2≤m≤n−1) among the n determination voltages, and calculate a difference between a value of each of the n−m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n−m determination voltages.

Dependencies are inferred from the claim text.