Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorShinji SUZUKI
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device according to an embodiment includes a memory cell array having plural memory cells that can be set to any one of plural different threshold voltages, plural bit lines connected to the plural memory cells respectively, a word line connected to gates of the plural memory cells, a control unit configured to execute a write sequence for repetitively performing plural loops including a set of a program operation of writing data into the memory cells and a verify operation of verifying data written in the memory cells to write predetermined data in the memory cells MT, and prior to execution of the write sequence, the control unit corrects the write sequence based on a result of performing the preliminary program operation and the detection verify operation on the memory cells.
Claims10
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells each of which can be set to any one of at least four different threshold voltages;
- a plurality of bit lines connected to the plurality of memory cells respectively;
- a word line connected to gates of the plurality of memory cells;
- and
- a control unit configured to execute a write sequence to write predetermined data into the memory cells, the write sequence including a plurality of loops each comprising a set of a program operation to write data into the respective memory cells and a verify operation to verify the data written in the respective memory cells,
- wherein prior to execution of the write sequence, the control unit performs a preliminary program operation and a detection verify operation on the memory cells, and corrects the write sequence based on a result of the detection verify operation.
Dependencies are inferred from the claim text.