Power aware programmable negative bit line control

A method for selectively boosting a differential bit line voltage on a bit line pair in a memory device, comprising:

• receiving access requests at the memory device operating according to an initial power supply voltage;
• in response to detection of a change of a power supply voltage, selecting between enabling and disabling a negative bit line enable signal to the memory device based at least in part on the power supply voltage;
• generating the negative bit line enable signal in response to detecting an active operating power state, when the initial power supply voltage is below a first threshold, and in response to detecting an inactive operating power state, when the initial power supply voltage is above a second threshold higher than the first threshold;
• and
• driving a selected bit line of a bit line pair to a negative voltage in response to the negative bit line enable signal.

A memory comprising:

• true and complement bit lines forming a bit line pair;
• a plurality of memory cells coupled to the true and complement bit lines, each memory cell for storing a memory bit according to a differential voltage between the true and complement bit lines when selected during a write cycle;
• and
• a write driver coupled to the true and complement bit lines comprising:
• a first write data driver for providing a true write data signal to the true bit line at a high voltage when a true data signal is in a first logic state, at a ground voltage when the true data signal is in a second logic state and a negative bit line enable signal is inactive, and at a voltage below the ground voltage when the true data signal is in the second logic state and the negative bit line enable signal is active;
• a second write data driver for providing a complement write data signal to the complement bit line at the high voltage when a complement data signal is in the first logic state, at the ground voltage when the complement data signal is in the second logic state and the negative bit line enable signal is inactive, and at the voltage below the ground voltage when the complement data signal is in the second logic state and the negative bit line enable signal is active;
• and
• a control circuit for providing the negative bit line enable signal in an active state when a power supply voltage is below a first threshold, and in an inactive state when the power supply voltage is above a second threshold higher than the first threshold.