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US 2020/0090735 A1Published application
Memory circuit configuration
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus LU
Life of this patent
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Abstract
A circuit includes a first cell in a first row of a memory array, a second cell in a second row of the memory array, and a data line perpendicular to the first row and the second row, intersecting each of the first cell and the second cell, and electrically coupled with each of the first cell and the second cell. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a read operation on the first row.
Claims20
A circuit comprising:
- a first cell in a first row of a memory array;
- a second cell in a second row of the memory array;
- and
- a data line perpendicular to the first row and the second row, intersecting each of the first cell and the second cell, and electrically coupled with each of the first cell and the second cell,
- wherein the circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a read operation on the first row.
2 more elements
A circuit comprising:
- a first cell in a first row of a memory array, the first cell comprising a first switching device coupled between a data line and a first node having a voltage level;
- and
- a second cell in a second row of the memory array, the second cell comprising a second switching device coupled between the data line and a second node having the voltage level,
- wherein the circuit is configured to simultaneously bias the data line to the voltage level through the first switching device and the second switching device.
1 more element
A circuit comprising:
- a first address decoding circuit configured to receive an address signal and activate a first row of a memory array in response to the address signal corresponding to an address of the first row;
- and
- a second address decoding circuit configured to receive the address signal and, in response to the address signal matching address information stored in a storage device corresponding to the address of the first row, activate a second row of the memory array simultaneously with the first address decoding circuit activating the first row.
Dependencies are inferred from the claim text.