Memory Device Comprising An Electrically Floating Body Transistor

An integrated circuit comprising:

• a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
• an electrically floating body region comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with said electrically floating body region;
• a drain region comprising said second conductivity type in physical contact with said electrically floating body region and spaced apart from said source line region;
• a charge injector region, wherein said charge injector region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region and said drain region;
• and
• a gate region positioned in between said source line region and said drain region, the gate region being positioned between said source line region and said charge injector region, and the gate region being positioned between said drain region and said charge injector region;
• wherein said electrically floating body region is configured to have more than one stable state through an application of a bias on said charge injector region;
• wherein said charge injector region is commonly connected to at least two of said semiconductor memory cells;
• and
• a control circuit configured to apply a bias to said charge injector region.

An integrated circuit comprising:

• a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said memory cells is connected in series with an access device, respectively, and wherein each said memory cell includes:
• an electrically floating body region comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with said electrically floating body transistor;
• a drain region comprising said second conductivity type in physical contact with said electrically floating body region and spaced apart from said source line region;
• and
• a charge injector region, wherein said charge injector region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region and said drain region;
• a gate region positioned in between said source line region and said drain region, the gate region being positioned between said source line region and said charge injector region, and the gate region being positioned between said drain region and said charge injector region;
• wherein said electrically floating body region is configured to have more than one stable state through an application of a bias on said charge injector region;
• wherein said charge injector region is commonly connected to at least two of said semiconductor memory cells;
• and
• a control circuit configured to apply a bias to said charge injector region.