Memory performing refresh operation and operation method of the same
AssigneeSK hynix Inc.
InventorYo-Sep LEE
Life of this patent
Estimating the term…
Abstract
A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.
Claims13
A memory comprising:
- first to Nth areas refreshed based on first to Nth refresh control signals, respectively;
- a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal;
- an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal;
- and
- a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.
An operation method of a memory including first to Nth areas (where N is an integer equal to or greater than 2), the operation method comprising:
- sequentially refreshing the first to Nth areas for a Kth address (where K is an integer equal to or greater than 0);
- starting a refresh operation for a (K+1)t11 address in the first area before a refresh operation for the Kth address in the Nth area is completed;
- and
- sequentially refreshing the second to Nth regions for the (K+1)th address.
A memory comprising:
- a plurality of memory banks that are grouped for a refresh operation and refreshed based on a row address and a plurality of refresh control signals each corresponding to each group of the plurality of memory banks;
- and
- a control signal generation circuit suitable for generating the plurality of refresh control signals sequentially activated based on a refresh signal, and changing the row address corresponding to each round for activations of the plurality of refresh control signals,
- wherein an activation section of the last refresh control signal among the plurality of refresh control signals and an activation section of the first refresh control signal among the plurality of refresh control signals for a subsequent round partially overlap with each other.
Dependencies are inferred from the claim text.