Memory module including register clock driver detecting address frequently accessed
AssigneeSamsung Electronics Co., Ltd.
InventorsJONGPIL SON, Wooyeong Cho
Life of this patent
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Abstract
A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.
Claims20
A memory module comprising:
- a plurality of memory devices each comprising a memory cell array;
- and
- a register clock driver connected to the plurality of memory devices,
- wherein the register clock driver is configured to:
- latch a first address among addresses corresponding to word lines of the memory cell array received from a memory controller;
- convert a first command for refreshing the memory cell array to a second command, the first command being received from the memory controller;
- and
- transmit the second command instead of the first command and the first address to the plurality of memory devices.
A memory module comprising:
- a plurality of memory devices;
- and
- a register clock driver configured to receive a plurality of first commands for refreshing a memory cell array of each of the plurality of memory devices from a memory controller, convert one first command among the plurality of first commands to a second command, and transmit remaining first commands, which are not converted, of the plurality of first commands and the second command to the plurality of memory devices,
- wherein the register clock driver is further configured to receive a first row address corresponding to a first word line of the memory cell array from the memory controller at least once or more, latche the first row address, and transmit the first row address to the plurality of memory devices together with the second command.
A memory module comprising:
- a plurality of memory devices each comprising a memory cell array;
- and
- a register clock driver configured to receive a plurality of activate commands from a memory controller and transmit the plurality of activate commands to the plurality of memory devices,
- wherein the register clock driver is configured to:
- count the number of times that a first address corresponding to a first word line, which is activated by first activate commands among the plurality of activate commands, of the memory cell array is repeatedly received;
- latch the first address based on a result of the counting;
- convert one first command of a plurality of first commands for refreshing the memory cell array to a second command;
- and
- transmit the second command instead of the one first command of the plurality of first commands and the first address to the plurality of memory devices.
Dependencies are inferred from the claim text.