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US 2020/0090721 A1Published application
Word line decoder memory architecture
AssigneeSpin Memory, Inc.
InventorsNeal BERGER, Susmita KARMAKAR, Benjamin LOUIE
Life of this patent
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Abstract
A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.
Claims20
A memory device comprising:
- a plurality of word lines;
- a level shifter latch configured to receive a plurality of decoded address signals upon a first state of a clock signal and to output a plurality of word line signals, wherein the level shifter latch includes
- a first inverter including an input configured to receive one of the plurality of decoded address signals;
- a second inverter including an input coupled to an output of the first inverter;
- a first transmission gate including a first terminal coupled to the output of the first inverter, and a second terminal configured to receive a short pulse clock signal, wherein the short pulse clock signal is based on a rising edge of a system clock and has a shorter pulse width then the pulse width of the system clock;
- a second transmission gate including a first terminal coupled to an output of the second inverter, and a second terminal configured to receive the short pulse clock signal;
- third inverter circuit including an input coupled to a third terminal of the first transmission gate, power terminals coupled between a high voltage source, and an output terminal configured to output a first one of the plurality of word line signals;
- and
- a fourth inverter circuit including a input coupled to a third terminal of the second transmission gate and the output of first inverter circuit, power terminals coupled between the high voltage source, and an output coupled to the input of the first inverter circuit;
- and
- a word line driver configured to receive the plurality of word line signals and drive the plurality of word line signals on corresponding ones of the plurality of word lines.
8 more elements
(canceled)
(canceled)
A device comprising:
- a first inverter including an input configured to receive a signal, wherein the first inverter operates from a first supply potential;
- a second inverter including an input coupled to an output of the first inverter, wherein the second inverter operates from a first supply potential;
- a first transmission gate including a control terminal configured to receive a clock signal and an input coupled to the output of the first inverter;
- a second transmission gate including a control terminal configured to receive the clock signal and an input coupled to the output of the second inverter;
- a latch including a third inverter cross coupled to a fourth inverter, wherein an input of the third inverter is coupled to an output of the first transmission gate and an output of the fourth inverter, wherein an input of the fourth inverter is coupled to an output of the second transmission gate and an output of the third inverter, and wherein the latch operates from a second supply potential that is greater than the first supply potential;
- and
- an inverting driver including an input coupled to an output of the third inverter and an output configured to output a drive signal, wherein the inverting driver operates from the second supply potential.
4 more elements
A memory device comprising:
- a memory cell array including a plurality of word lines;
- an address buffer configured to buffer a plurality of address signals, wherein the address buffer operates from a first supply potential;
- an address decoder circuit configured to receive the buffered plurality of address signals and output a plurality of decoded address signals, wherein the address decoder operates from the first supply potential;
- a level shifter latch configured to receive the plurality of decoded address signals upon a first state of a clock signal and to output a plurality of word line signals, wherein the level shifter latched operates form a second supply potential that is greater than the first supply potential, and wherein the level shifter latch includes;
- a first inverter including an input configured to receive one of the plurality of decoded address signals;
- a second inverter including an input coupled to an output of the first inverter;
- a first transmission gate including a control terminal configured to receive the clock signal and an input coupled to the output of the first inverter;
- a second transmission gate including a control terminal configured to receive the clock signal and an input coupled to the output of the second inverter;
- and
- a latch including a third inverter cross coupled to a fourth inverter, wherein an input of the third inverter is coupled to an output of the first transmission gate and an output of the fourth inverter, wherein an input of the fourth inverter is coupled to an output of the second transmission gate and an output of the third inverter, and wherein the latch operates from a second supply potential that is greater than the first supply potential;
- and
- a word line driver configured to receive the plurality of word line signals and drive the plurality of word line signals on corresponding ones of the plurality of word lines, wherein the word line driver operates form the second supply potential.
9 more elements
(canceled)
Dependencies are inferred from the claim text.