Controller and method of operating the same
AssigneeSK hynix Inc.
InventorHo Jung YUN
Life of this patent
Estimating the term…
Abstract
Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay.
Claims16
A controller configured to control operations of a plurality of semiconductor memory devices, the controller comprising:
- a write pass determination component configured to receive training data written to the plurality of semiconductor memory devices, and determine whether write operations of the plurality of semiconductor memory devices have passed;
- an offset storage configured to update offsets based on the determinations of the write pass determination component, and store the updated offsets;
- and
- a tapped delay storage configured to update, based on the updated offsets, a plurality of tapped delays to be applied to the write operations of each of the plurality of semiconductor memory device, and store the plurality of updated tapped delays.
A controller for performing write test operations to at least one memory device, the controller comprising:
- a processor configured to control the at least one memory device to perform write operations of writing test data thereto, each of the write operations being performed according to respective tapped delays between a data signal and a data strobe signal;
- a write pass determination component configured to determine success or failure of each of the write operations;
- an offset storage configured to store an offset at each successive failure of the write operations;
- and
- a tapped delay storage configured to store the tapped delay increased by the amount of the offset,
- wherein the processor is, during the write operations of the at least one memory device, configured to:
- determine a minimum pass tapped delay by increasing stepwise, from a minimum tapped delay, the tapped delay by the amount of the offset after each failure of the write operations;
- determine an optimized tapped delay greater than or equal to the minimum pass tapped delay.
A controller for performing write test operations to at least one memory device, the controller comprising:
- a processor configured to control the at least one memory device to perform write operations of writing test data thereto, each of the write operations being performed according to respective tapped delays between a data signal and a data strobe signal;
- a write pass determination component configured to determine success or failure of each of the write operations;
- an offset storage configured to store an offset at each successive failure of the write operations;
- and
- a tapped delay storage configured to store the tapped delay decreased by the amount of the offset,
- wherein the processor is, during the write operations of the at least one memory device, configured to:
- determine a maximum pass tapped delay by decreasing stepwise, from a maximum tapped delay, the tapped delay by the amount of the offset after each failure of the write operations;
- and
- determine an optimized tapped delay smaller than or equal to the maximum pass tapped delay.
Dependencies are inferred from the claim text.