Storage device

A storage device comprising:

• a controller;
• a first memory chip including a first address setting circuit configured to,
• receive an address setting command from the controller to generate a first initializing signal,
• receive a signal from outside to generate a first input signal,
• set a first delay time based on the first initializing signal,
• delay the first input signal by the first delay time to generate a first output signal,
• delay the first initializing signal by a second delay time to generate a first clock signal,
• determine a first output time point based on the first clock signal, and
• output a level of the first input signal at the first output time point as a first value of
• a first address of the first memory chip;
• and
• a second memory chip including a second address setting circuit configured to receive the first output signal from the first address setting circuit.

A memory chip comprising:

• a first input pad configured to receive a first input signal;
• a first initializing circuit configured to provide a first initializing signal;
• a first input delay circuit configured to delay the first input signal based on the first initializing signal;
• a first ring oscillator configured to generate a first clock signal and a second clock signal such that the second clock signal is the first clock signal delayed by a first time;
• a first latch configured to store the first input signal based on the first clock signal;
• a second latch configured to store the first input signal based on the second clock signal;
• and
• a first clock controller configured to provide the first clock signal and the second clock signal to the first latch and the second latch, respectively.