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US 2020/0090710 A1Published application
Data latch circuit and semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsKeisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
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Abstract
A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
Claims26
A data latch circuit, comprising:
- a first n-channel transistor;
- and
- a first p-channel transistor,
- a gate of the first n-channel transistor and a gate of the first p-channel transistor being a common gate.
1 more element
A semiconductor memory device, comprising:
- a first sense amplifier circuit;
- and
- a second sense amplifier circuit,
- the first sense amplifier circuit and the second sense amplifier circuit each including a data latch circuit including an n-channel transistor,
- a gate of the n-channel transistor of the first sense amplifier circuit and a gate of the n-channel transistor of the second sense amplifier circuit being a common gate.
2 more elements
A data latch circuit, comprising:
- a first semiconductor substrate;
- an n-well provided on the first semiconductor substrate;
- a p-well provided on the first semiconductor substrate and arranged to be adjacent to the n-well in a first direction;
- first to sixth p-type layers provided on the n-well and arranged along a second direction crossing the first direction;
- first to fifth n-type layers provided on the p-well and arranged along the second direction;
- a first gate provided in a region directly above a portion of the n-well between the first p-type layer and the second p-type layer;
- a second gate provided in a region directly above a portion of the p-well between the first n-type layer and the second n-type layer;
- a third gate provided in a region directly above a portion of the n-well between the second p-type layer and the third p-type layer and in a region directly above a portion of the p-well between the second n-type layer and the third n-type layer;
- a fourth gate provided in a region directly above a portion of the n-well between the fourth p-type layer and the fifth p-type layer and in a region directly above a portion of the p-well between the third n-type layer and the fourth n-type layer;
- a fifth gate provided in a region directly above a portion of the n-well between the fifth p-type layer and the sixth p-type layer;
- and
- a sixth gate provided in a region directly above a portion of the p-well between the fourth n-type layer and the fifth n-type layer.
9 more elements
A data latch circuit, comprising:
- a first semiconductor substrate;
- a first p-well provided on the first semiconductor substrate;
- a second p-well provided on the first semiconductor substrate and separated from the first p-well in a first direction;
- an n-well provided on the first semiconductor substrate and disposed between the first p-well and the second p-well;
- first to third n-type layers provided on the first p-well and arranged along a second direction crossing the first direction;
- fourth to sixth n-type layers provided on the second p-well and arranged along the second direction;
- first and second p-type layers provided on the n-well and arranged along the second direction;
- third and fourth p-type layers provided on the n-well and arranged along the second direction;
- a first gate provided in a region directly above a portion of the first p-well between the first n-type layer and the second n-type layer;
- a second gate provided in a region directly above a portion of the first p-well between the second n-type layer and the third n-type layer and in a region directly above a portion of the n-well between the first p-type layer and the second p-type layer;
- a third gate provided in a region directly above a portion of the n-well between the third p-type layer and the fourth p-type layer and in a region directly above a portion of the second p-well between the fourth n-type layer and the fifth n-type layer;
- and
- a fourth gate provided in a region directly above a portion of the second p-well between the fifth n-type layer and the sixth n-type layer.
10 more elements
Dependencies are inferred from the claim text.