Apparatuses and methods for plate coupled sense amplifiers
AssigneeMicron Technology, Inc.
InventorsADAM S. EL-MANSOURI, John D. Porter
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Abstract
Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.
Claims21
An apparatus comprising:
- a sense amplifier comprising a hysteresis inverter, the sense amplifier configured to read a voltage from a memory cell, monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage activates the hysteresis inverter.
A method comprising:
- reading a logical value from a memory cell as a voltage, wherein the voltage is coupled to a plate voltage;
- changing the plate voltage from a first voltage to a second voltage;
- and
- determining the logical value represented by the voltage read from the memory cell based on a time when the voltage read from the memory cell changes to a trigger voltage.
An apparatus comprising:
- a plurality of memory cells each containing a physical signal corresponding to a logical value, wherein the plurality of memory cells are disposed along a plurality of bit lines;
- a plate coupled to the plurality of cells, the plate having a plate voltage configured to ramp to a limit voltage;
- a plurality of sense amplifiers, wherein each sense amplifier is coupled to one of the plurality of bit lines, each of the sense amplifiers configured to read the physical signal from one of the memory cells of the coupled bit line as a data voltage and amplify the data voltage to an output voltage, wherein the data voltage is coupled to the plate voltage and changes towards the limit voltage as the plate voltage ramps to the limit voltage;
- and
- a plurality of latch circuits, each of the plurality of latch circuits coupled to a respective sense amplifier, wherein the latch circuits latch the output voltage from the respective sense amplifier at a cutoff time.
An apparatus comprising:
- a first gut node coupled to the input of a hysteresis inverter, and selectively coupled to a limit voltage through a first switch;
- a second gut node coupled to an output of the hysteresis inverter;
- and
- a digit line selectively coupled to the first gut node through a transistor, wherein a voltage of the first gut node is selectively set to the reference voltage through the first switch, the voltage of the first gut node changes from the limit voltage due to coupling through the transistor to a voltage of the digit line, and the hysteresis inverter changes a voltage of the second gut node when the voltage of the first gut node passes a threshold voltage.
Dependencies are inferred from the claim text.