Shift register circuit, driving method, gate driving circuit and display device

A shift register circuit comprising:

• a first level output terminal configured to output a first level;
• a second level output terminal configured to output a second level;
• a third level output terminal configured to output a third level;
• a first transistor having a gate electrode being coupled to a pull-down node, a first electrode being coupled to a pull-up node, and a second electrode being coupled to the second level output terminal and configured to receive the second level;
• a second transistor having a gate electrode being coupled to the pull-up node, a first electrode being coupled to the pull-down node, and a second electrode being coupled to the second level output terminal;
• a third transistor having a gate electrode being coupled to the pull-up node, a first electrode being coupled to a first clock signal output terminal, a second electrode being coupled to a carry signal output terminal;
• a fourth transistor having a gate electrode being coupled to the pull-down node, a first electrode being coupled to the carry signal output terminal, and a second electrode being coupled to the third level output terminal;
• a fifth transistor having a gate electrode being coupled to a second clock signal output terminal, a first electrode being coupled to the second clock signal output terminal, and a second electrode being coupled to the pull-down node;
• a sixth transistor having a gate electrode being coupled to the pull-up node, a first electrode being coupled to the first clock signal output terminal, and a second electrode being coupled to the gate drive signal output terminal, and
• a seventh transistor having a gate electrode being coupled to the pull-down node, a first electrode being coupled to the gate drive signal output terminal, and a second electrode being coupled to the third level output terminal;
• an eighth transistor having a gate electrode being coupled to the second clock signal output terminal, a first electrode being coupled to the gate drive signal output terminal, and a source electrode being coupled to the third level output terminal;
• a ninth transistor having a gate electrode being coupled to a carry signal output terminal of an adjacent previous level shift register circuit and a first electrode being coupled to the first level output terminal;
• a tenth transistor having a gate electrode being coupled to the carry signal output terminal of the adjacent previous level shift register circuit, a first electrode being coupled to a second electrode of the ninth transistor, and a second electrode being coupled to the pull-up node;
• an eleventh transistor having a gate electrode being coupled to a carry signal output terminal of an adjacent next level shift register, and a first electrode being coupled to the pull-up node;
• a twelfth transistor having a gate electrode being coupled to the carry signal output terminal of the adjacent next level shift register, a first electrode being coupled to a first electrode of the eleventh transistor, and a second electrode being coupled to the second level output terminal;
• a first storage capacitor coupled between the pull-up node and one of the carry signal output terminal and the gate drive signal output terminal;
• and
• a second storage capacitor having a first end being coupled to the pull-down node, and a second end being coupled to the third level output terminal;
• wherein when the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth are n-type transistors, the third level is a first low level, the second level is a second low level, the second low level is less than the first low level, and the first level is a high level;
• and
• when the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth are p-type transistors, the third level is a first low level, the second level is a second low level, the second low level is greater than the first low level, and the first level is a high level.