Defect inspection apparatus and defect inspection method

An apparatus for classifying a defect, the apparatus comprising:

• a memory storage;
• and
• a processing unit coupled to the memory storage, wherein the processing unit is configured to:
• acquire pattern data indicative of one or more patterns implemented on a wafer from a storage device,
• respectively assign a first set of numbers to each of the one or more patterns indicated by the pattern data, and respectively assign a second set of numbers to each of one or more circuit patterns indicated by design information, the design information including a portion of a figure indicated by design data that corresponds to the pattern data,
• generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers,
• perform classification of a defect type for the pattern data based on the relation information to generate a classification result, and
• send the classification result to a device.

An apparatus for inspecting a defect, the apparatus comprising:

• a memory storage;
• and
• a processing unit coupled to the memory storage, wherein the processing unit is configured to:
• acquire pattern data indicative of one or more patterns implemented on a wafer from a storage device,
• respectively assign a first set of numbers to each of the one or more patterns indicated by the pattern data,
• respectively assign a second set of numbers to each of one or more circuit patterns indicated by design information, the design information including a portion of a figure indicated by design data that corresponds to the pattern data,
• generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers,
• verify whether or not the one or more patterns indicated by the pattern data constitute a defect in a circuit of the wafer based on the relation information to generate a verification result, and
• send the verification result to a device.

A defect inspection method comprising:

• acquiring pattern data indicative of one or more patterns implemented on a wafer from a storage device;
• clipping a portion that corresponds to the pattern data from a figure indicated by design data to generate design information that indicates one or more circuit patterns;
• respectively assigning a first set of numbers to each pattern indicated by the pattern data and respectively assigning a second set of numbers to each of the circuit patterns indicated by the design information;
• generating relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers;
• verifying whether or not the one or more patterns indicated by the pattern data constitute a defect in a circuit of the wafer based on the relation information to generate a verification result;
• and
• sending the verification result to a device.

A data storage medium storing non-transitory processor-executable instructions which, when executed by a processor, cause the processor to perform a defect inspection method comprising:

• acquiring pattern data indicative of one or more patterns implemented on a wafer from a storage device;
• clipping a portion that corresponds to the pattern data from a figure indicated by design data to generate design information that indicates one or more circuit patterns;
• respectively assigning a first set of numbers to each pattern indicated by the pattern data and respectively assigning a second set of numbers to each of the circuit patterns indicated by the design information;
• generating relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers;
• verifying whether or not the one or more patterns indicated by the pattern data constitute a defect in a circuit of the wafer based on the relation information to generate a verification result;
• and
• sending the verification result to a device.