System and method for forming integrated device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYU-TAO YANG, YUNG-CHOW PENG
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Abstract
A method for forming an integrated device includes the following operations. A first circuit layout is provided. The first circuit layout includes a first device and a connecting portion. A first voltage level is applied to the first circuit layout. The first circuit layout is analyzed according to the first voltage level to determine if a failing signal occurs in the first circuit layout. The first device is analyzed when the failing signal occurs. It is determined, according to a second voltage level, whether a violation occurs in the first device. The first circuit layout is modified when a violation occurs.
Claims20
A method for forming an integrated device, the method comprising:
- obtaining a first circuit layout comprising a first device and a connecting portion;
- applying a first voltage level to the first circuit layout;
- analyzing the first circuit layout according to the first voltage level to determine if a failing signal occurs in the first circuit layout;
- analyzing the first device when the failing signal occurs;
- and
- determining, according to a second voltage level, if a violation occurs in the first device.
A method for forming an integrated device, the method comprising:
- obtaining a first circuit layout comprising a plurality of conductive lines;
- applying a first voltage level to the first circuit layout;
- analyzing the first circuit layout according to the first voltage level to determine if a failing signal occurs in the first circuit layout;
- analyzing a first pitch of the conductive lines when the failing signal occurs;
- and
- determining, according to a second voltage level, if a violation occurs in the first pitch.
A system for forming an integrated device, comprising:
- a designing tool, arranged to provide a first circuit layout having a first conductive line and a second conductive line spaced apart from each other by a first pitch;
- a pitch analyzing tool configured to, in response to a failing signal which indicates that the first pitch is out of an allowable range corresponding to a first voltage difference, determine whether the first pitch is out of an allowable range corresponding to a second voltage difference different from the first voltage difference, wherein the first voltage difference and the second voltage difference are individually associated with a testing voltage of a design rule;
- a modifying tool, configured to generate a modified first circuit layout by modifying the first pitch of the first circuit layout when the pitch analyzing tool indicates that the first pitch is out of the allowable range corresponding to the second voltage difference;
- and
- a fabricating tool, arranged to generate the integrated device according to the modified first circuit layout.
Dependencies are inferred from the claim text.