Capacitance extraction method for semiconductor sadp metal wires

A computer program product for manufacturing a multi-level integrated circuit (IC), the computer program product comprising

• a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by the computer to cause the computer to perform a method comprising:
• analyzing, using a computer system, a multi-level integrated circuit design layout;
• extracting, using the computing system, a parasitic capacitance of structures in said multi-level IC design layout, said structures including a wire level having a plurality of metal wires to be manufactured according to a self-aligned double-patterning (SADP) manufacturing process, said wire level situated above one or more lower layers of conductive structures and situated below one or more upper layers of conductive structures, said extracting resulting in a capacitive network of wires in said IC design layout;
• selecting a target metal wire from said plurality of metal wires at said wire level, said selected target metal wire having one or more parallel situated floating metal wires on at least one side thereof, said capacitive network comprising:
• capacitance component values for said target metal wire at said SADP metal wire layer, capacitance component values of said floating metal wires, a node of said selected target metal wire, and nodes of the floating metal wires;
• eliminating, using one or more processors of said computing system, the nodes of the floating metal wires from the capacitive network to reduce the size of the capacitive network;
• simulating, using a circuit simulator run at said computer system, a circuit performance involving the selected target metal wire of the capacitive network;
• and
• repeating, at the computing system, from said IC design layout, cycles of parasitic capacitance extracting, capacitance-network size reduction, and said simulating to optimize the multi-level IC design layout.