Elmore Delay Time (EDT)-Based Resistance Model
AssigneeSynopsys, Inc.
InventorRalph Benhart IVERSON
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Abstract
We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.
Claims20
A computer-implemented method executed by an integrated circuit design tool for modeling resistance of a gate terminal of a transistor for implementation on an integrated circuit, the transistor having at least one channel region, the method including:
- specifying a structure of the gate terminal in a data structure in memory using a three-dimensional (3D) coordinate system;
- for each of a plurality of volume elements in the specified structure, determining an Elmore delay time (EDT) and storing the EDT in a database in the memory;
- for those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, determining an average EDT (aEDT) based on the EDT and storing the aEDT in the database in the memory;
- and
- executing a program of instructions to generate point-to-point resistance values of the gate terminal as a function of the aEDT and a capacitance of the gate terminal.
An integrated circuit design tool for modeling resistance of a gate terminal of a transistor, the transistor having at least one channel region, the tool comprising:
- a computer system including a processor or processors and memory, the memory storing instructions executable by the computer system for a process including:
- specifying a structure of the gate terminal in a data structure in memory using a three-dimensional (3D) coordinate system;
- for each of a plurality of volume elements in the specified structure, determining an Elmore delay time (EDT) and storing the EDT in a database in the memory;
- for those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, determining an average EDT (aEDT) based on the EDT and storing the aEDT in the database in the memory;
- and
- executing a program of instructions to generate point-to-point resistance values of the gate terminal as a function of the aEDT and a capacitance of the gate terminal.
A computer program product comprising a non-transitory computer readable data storage medium storing a program of instructions to perform the method comprising:
- specifying a structure of the gate terminal in a data structure in memory using a three-dimensional (3D) coordinate system;
- for each of a plurality of volume elements in the specified structure, determining an Elmore delay time (EDT) and storing the EDT in a database in the memory;
- for those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, determining an average EDT (aEDT) based on the EDT and storing the aEDT in the database in the memory;
- and
- executing a program of instructions to generate point-to-point resistance values of the gate terminal as a function of the aEDT and a capacitance of the gate terminal.
Dependencies are inferred from the claim text.