Adjusting interrupt priorities

A system comprising:

• a memory device;
• a core to execute interrupt latency control unit (ILCU) software, the core coupled to the memory device;
• and
• an interrupt controller circuitry coupled to the core and the memory device, wherein the interrupt controller circuitry comprises:
• a first register to store a first time value at which a first interrupt is received at the interrupt controller circuitry;
• and
• a second register to store a second time value at which the first interrupt is delivered to the core by the interrupt controller circuitry, wherein the ILCU software is to:
• read the first time value in the first register and the second time value in the second register in response to the core receiving the first interrupt, the first interrupt having a first interrupt priority for a first type of interrupt;
• determine an amount of time the first interrupt was pending at the interrupt controller circuitry before the first interrupt was received by the core using the first time value and the second time value;
• determine interrupt configuration information that adjusts the first interrupt priority of a subsequent interrupt of the first type to a second interrupt priority that is different than the first interrupt priority;
• and
• send the interrupt configuration information to the interrupt controller circuitry, wherein the interrupt controller circuitry is to:
• receive the subsequent interrupt of the first type;
• and
• adjust the first interrupt priority of the subsequent interrupt to the second interrupt priority using the interrupt configuration information.

A method comprising:

• reading, by a core from a first register in an interrupt controller circuitry, a first time value at which a first interrupt is received at the interrupt controller circuitry;
• reading, by the core from a second register in the interrupt controller circuitry, a second time value at which the first interrupt is delivered to the core by the interrupt controller circuitry, the first interrupt having a first interrupt priority for a first type of interrupt;
• determining, by the core, an amount of time the first interrupt was pending at the interrupt controller circuitry before the first interrupt was received by the core using the first time value and the second time value;
• generating, by the core, interrupt configuration information to adjust the first interrupt priority of a subsequent interrupt of the first type to a second interrupt priority that is different than the first interrupt priority;
• and
• sending, by the core, the interrupt configuration information to the interrupt controller circuitry, wherein the interrupt controller circuitry is to receive the subsequent interrupt of the first type and adjust the first interrupt priority of the subsequent interrupt to the second interrupt priority using the interrupt configuration information.