US 2020/0089628 A1 · SOC CHIP AND METHOD FOR CONTROLLING BUS ACCESS

Abstract

A SoC chip includes: a bus mechanism including at least one MPU; an OTP memory configured to store bus access control information; a mode configuring module connected to at least one MPU and the OTP memory, the mode configuring module being configured to read the bus access control information from the OTP memory when the SoC chip is in a boot mode, and configure the MPU using the bus access control information, and the mode configuring module being further configured to enable the MPU and switch the SoC chip to a user mode upon configuration of the MPU. The bus access control information is stored by using the OTP memory, so that corresponding bus access control information may be written into the OTP memory according to requirements of various application scenarios, thereby being adapted to different application scenarios and having great flexibility.

Claims17

Dependent claims

A System-on-a-Chip SoC chip, comprising:

a bus mechanism comprising at least one Memory Protection Unit MPU;
an One Time Programable OTP memory configured to store bus access control information;
and
a mode configuring module configured to connect the at least one MPU to the OTP memory, the mode configuring module being configured to:
read the bus access control information from the OTP memory when the SoC chip is in a boot mode;
and
configure the MPU using the bus access control information;
wherein the mode configuring module is further configured to enable the MPU and switch the SoC chip to a user mode upon configuration of the MPU.

5 more elements

A method for controlling bus access, wherein the method is applied to a System-on-a-Chip SoC chip comprising:

a bus mechanism comprising at least one Memory Protection Unit MPU;
an One Time Programable OTP memory configured to store bus access control information;
and
a mode configuring module configured to connect the at least one MPU to the OTP memory;
wherein the method comprises:
reading, by the mode configuring module, the bus access control information from the OTP memory when the SoC chip is in a boot mode;
configuring, by the mode configuring module, the MPU using the bus access control information;
and,
enabling, by the mode configuring module, the MPU and switching the SoC chip to a user mode upon configuration of the MPU.

6 more elements

Dependencies are inferred from the claim text.

Soc chip and method for controlling bus access

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Soc chip and method for controlling bus access

Life of this patent

Abstract

Claims17