Multiple memory type memory module systems and methods
AssigneeMicron Technology, Inc.
InventorRichard C. Murphy
Life of this patent
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Abstract
The present disclosure provides methods, apparatuses, and systems for implementing and operating a memory module, for example, in a computing device that includes a network interface, which is coupled to a network to enable communication with a client device, and processing circuitry, which is coupled to the network interface via a data bus and programmed to perform operations based on user inputs received from the client device. The memory module includes memory devices, which may be non-volatile memory or volatile memory, and a memory controller coupled between the data bus and the of memory devices. The memory controller may be programmed to determine when the processing circuitry is expected to request a data block and control data storage in the memory devices.
Claims20
An apparatus, comprising:
- a plurality of memory devices, wherein:
- a first portion of the plurality of memory devices is implemented to provide volatile memory;
- and
- a second portion of the plurality of memory devices is implemented to provide non-volatile memory;
- and
- a memory controller comprising buffer memory, wherein:
- the buffer memory comprises static random-access memory;
- the memory controller is communicatively coupled to each of the plurality of memory devices;
- and
- the memory controller is configured to deterministically store data blocks in either the volatile memory on the apparatus or the non-volatile memory implemented on the apparatus based at least in part on when the data blocks are expected to be requested from the apparatus.
An apparatus, comprising:
- a memory module comprising a plurality of non-volatile memory devices and a plurality of volatile memory devices;
- and
- a memory controller communicatively coupled to the memory module, wherein the memory controller is configured to:
- predict whether a first data block comprising instructions executable by processing circuitry to provide a first virtual machine will be requested within a duration threshold;
- transfer the first data block from the plurality of non-volatile memory devices to the plurality of volatile memory devices when the first data block is stored in the plurality of non-volatile memory devices and the first data block is expected to be requested within the duration threshold;
- and
- bypass buffer memory implemented in the memory controller when the first data block is actually requested within the duration threshold to enable the memory module to output the first data block directly from the plurality of volatile memory devices.
An apparatus comprising:
- a memory sub-system comprising a non-volatile memory device, a volatile memory device and buffer memory;
- processing circuitry configured to:
- perform a first operation based at least in part on a first data block stored in a memory sub-system;
- and
- perform a second operation after the first operation based at least in part on a second data block stored in the memory sub-system;
- and
- a bus interface communicatively coupled to the processing circuitry, wherein the bus interface is configured to be communicatively coupled to the memory sub-system via a data bus to enable the processor to:
- receive the first data block from the memory sub-system in response to a first memory access request targeting the first data block;
- and
- receive the second data block from the memory sub-system along with the first data block in response to the first memory access request identifying the first data block when the processing circuitry is expected to target the second data block less than a duration threshold after the first data block.
Dependencies are inferred from the claim text.