Method, system, and apparatus for stress testing memory translation tables
AssigneeInternational Business Machines Corporation
InventorsManoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Abstract
Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.
Claims20
A method for testing a non-core memory management unit (“MMU”) in a processor, the method comprising:
- generating by the processor a first set of command tables containing a first set of virtual memory addresses and a first set of physical memory addresses;
- receiving at the non-core MMU a first plurality of transition requests that were generated based upon the first set of virtual memory addresses from the first set of command tables;
- translating by the non-core MMU translation requests that were generated based on the virtual memory addresses contained in the first command table, generating a page table using translations of the virtual addresses contained in the first command table;
- polling a first flag to determine if the non-core MMU has completed translating the plurality of translation requests;
- and
- invalidating the page table on a condition that the first flag indicates that the plurality of translation requests from the first command table have been translated and completed by the non-core MMU.
A method for testing a non-core memory management unit (“MMU”) disposed on a processor chip, wherein the non-core MMU is external to a processing core on the processor chip, the method comprising:
- polling by a non-core MMU tester a first flag to determine whether the non-core MMU is ready to receive a first set of translation requests that include a first set of virtual memory addresses;
- on a condition that the first flag indicates that the non-core MMU is ready to receive the first set of translation requests, transmitting the first set of translation requests from the MMU tester to the non-core MMU, wherein the first set of translation requests are based on a first command table;
- and
- receiving, at the MMU tester, a first set of memory translation results from the non-core MMU in response to the first set of translation requests;
- and
- comparing the first set of translation results to a previously received set of translation results and halting execution of the MMU tester on a condition that the first set of translation results match the previously received set of translation results.
A system, comprising:
- a computer processor;
- a MMU tester separate from the simulated processor chip, wherein the MMU tester is configured to generate a first set of translation requests based on a first command table containing a first set of virtual memory addresses and a first set of physical memory addresses;
- a communication link between the simulated processor chip and the MMU tester;
- and
- a memory containing a computer program that, when executed by the computer processor, performs an operation in a simulated computing environment, the operation comprising:
- simulating a non-core MMU in a simulated processor chip, wherein the non-core MMU is external to a processing core of the simulated processor chip;
- simulating a process for testing the non-core MMU comprising:
- generating the first command table containing the first set of virtual memory addresses and the first set of physical memory addresses;
- generating a page table based on the first command table, wherein the page table enables the non-core MMU to execute the first set of translation requests that were generated based on the virtual and physical memory addresses contained in the first command table by translating the first set of virtual memory address into the first set of physical memory addresses;
- polling a first flag to determine if the non-core MMU has completed the first set of translation requests;
- and
- invalidating the page table on a condition that the first flag indicates that the first set of translation requests have been completed by the non-core MMU.
Dependencies are inferred from the claim text.