Memory system, storage system and method of controlling the memory system

A storage system connectable to a host, comprising:

• a plurality of storage devices;
• a cache configured to cache a part of a multi-level mapping table which manages mapping between each of first type logical addresses designated by the host and each of second type logical addresses for accessing the plurality of storage devices;
• and
• a controller configured to control the plurality of storage devices and the cache,
• the multi-level mapping table including a plurality of tables corresponding to a plurality of hierarchical levels, each of the tables containing a plurality of address translation data portions, and each of the plurality of address translation data portions included in the table of each of the hierarchical levels covering a logical address range according to each hierarchical level, wherein
• the controller is configured to:
• execute, by referring to the address translation data portion corresponding to each of the hierarchical levels stored in the cache, an address resolution process for converting the first type logical address into the second type logical address and an address update process of updating the second type logical address;
• and
• set a priority for each of the hierarchical levels, on the basis of a degree of bias of reference for each of the hierarchical levels, the degree of bias of reference relating to the address translation data portion corresponding to each of the hierarchical levels stored in the cache, and execute an operation of preferentially caching each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with a low priority.

A method of controlling a memory system including a nonvolatile memory configured to store a multi-level mapping table for logical-to-physical address translation, and a cache configured to cache a part of the multi-level mapping table,

• the multi-level mapping table including a plurality of tables corresponding to a plurality of hierarchical levels, each of the tables containing a plurality of address translation data portions, and each of the plurality of address translation data portions included in the table of each of the hierarchical levels covering a logical address range according to each hierarchical level,
• the method comprising:
• executing, by referring to the address translation data portion corresponding to each of the hierarchical levels stored in the cache, an address resolution process for logical-to-physical address translation and an address update process of updating a physical address corresponding to a logical address;
• setting a priority for each of the hierarchical level, on the basis of a degree of bias of reference for each of the hierarchical level, the degree of bias of reference relating to the address translation data portion corresponding to each of the hierarchical levels stored in the cache;
• and
• executing an operation of preferentially caching each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with a low priority.