Cache coherent node controller for scale-up shared memory systems

A multiprocessor memory sharing system at least comprising two or more nodes, a first node, a second node and optionally an interconnect switch, each node comprises a group of CPU's and an FPGA Node Controller, the first node comprises a first group of CPU's and at one first FPGA Node Controller configured to execute transactions directly or through the optional interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU's running a single instance of an operating system, where at least one of the FPGA Node Controllers at least comprises:

• a) at least one Coherent Interface configured to connect the FPGA Node Controller to one or more CPU's within the same node;
• b) a CPU interface unit configured to translate transactions specific to a particular CPU architecture into a global cache coherence protocol;
• c) a remote memory protocol engine, RMPE, configured to handle memory transactions that are destined to operate on memory connected with CPU's that are located on another side of a Coherent Interface Fabric, the RMPE is controlled by microcode firmware and programmed to be compliant with the cache coherence protocol of the particular CPU architecture;
• d) a local memory protocol engine, LMPE, specifically designed to handle memory transactions through executing microcode firmware and it is configured to handle all memory transactions that are directed from an external CPU to the memory connected to the CPU's local to the Node Controller;
• and
• e) an interconnect fabric Unit, configured to link the FPGA Node Controllers to other nodes in the multiprocessor memory sharing system of nodes, and.