Memory system

A method for controlling a memory device,

• the memory device comprising:
• a plurality of first memory cells each storing data based on a threshold voltage;
• a plurality of first bit lines connected to the plurality of first memory cells;
• a plurality of second memory cells each storing data based on a threshold voltage;
• a plurality of second bit lines connected to the plurality of second memory cells;
• a word line connected to the plurality of first and second memory cells;
• and
• a driver configured to apply a voltage to the word line,
• the method comprising:
• upon receipt of a command set including a first command for instructing a first operation to be performed and a second command for instructing a read operation to be performed, causing the driver to sequentially apply, to the word line:
• a plurality of first read voltages to read data from the first memory cells,
• a second read voltage within a voltage range of the first read voltages to read data from the first memory cells,
• a plurality of third read voltages to read data from the second memory cells, and
• a fourth read voltage within a voltage range of the third read voltages to read data from the second memory cells.

A memory system comprising:

• a semiconductor memory that includes:
• a plurality of first memory cells each storing data based on a threshold voltage,
• a plurality of first bit lines connected to the plurality of first memory cells,
• a plurality of second memory cells each storing data based on a threshold voltage,
• a plurality of second bit lines connected to the plurality of second memory cells,
• a word line connected to the plurality of first and second memory cells, and
• a driver configured to apply a voltage to the word line;
• and
• a memory controller that includes:
• a processor configured to control the semiconductor memory, and
• a first circuit configured to perform error correction of read data output from the semiconductor memory, wherein:
• in response to a first command set sent from the memory controller, the driver in the semiconductor memory sequentially applies, to the word line,
• a plurality of first read voltages to read data from the first memory cells,
• a second read voltage within a voltage range of the first read voltages to read data from the first memory cells,
• a plurality of third read voltages to read data from the second memory cells, and
• a fourth read voltage within a voltage range of the third read voltages to read data from the second memory cells;
• first data which are read from the first memory cells using the second read voltage and second data which are read from the second memory cells using the fourth read voltage are output to the memory controller;
• in response to the first data and the second data output from the semiconductor memory,
• the first circuit performs the error correction on the first data and on the second data, and
• the memory controller sends a second command set to the semiconductor memory;
• in response to the second command set sent from the memory controller, the driver in the semiconductor memory sequentially applies, to the word line,
• a plurality of fifth read voltages to read data from either one of the first memory cells or the second memory cells, and
• a sixth read voltage within a voltage range of the fifth read voltages to read data from the either one of the first memory cells or the second memory cells;
• and
• third data which are read from the either one of the first memory cells or the second memory cells are output to the memory controller.