Error Detection Within An Integrated Circuit Chip
AssigneeUltraSoC Technologies Ltd.
InventorGajinder Panesar
Life of this patent
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Abstract
A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.
Claims20
A method of performing error detection within an integrated circuit chip, comprising:
- analysing transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a transaction contains a data error;
- scanning a memory of the integrated circuit chip coupled to the interconnect circuitry to detect whether there is a data error stored in the memory;
- and
- in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, performing a dedicated action indicative of a data error.
An integrated circuit chip, comprising:
- interconnect circuitry configured to transport messages;
- a memory coupled to the interconnect circuitry;
- and
- detection circuitry configured to:
- analyse transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether there is a data error stored in the memory;
- scan the memory to detect whether data stored in the memory contains an error;
- and
- in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or an error in the data stored in the memory, perform a dedicated action indicative of a data error.
Dependencies are inferred from the claim text.