Memory device and method for handling interrupts thereof
AssigneeWinbond Electronics Corp.
InventorsCheng-Han LEE, Chien-Ti HOU, Ying-Te TU
Life of this patent
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Abstract
A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.
Claims20
A memory device, comprising:
- a memory cell array;
- a monitoring circuit, configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array;
- and
- an event-checking circuit, configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit,
- in response to the event-checking circuit determining to assert the interrupt signal, the event-checking circuit directly transmits the interrupt signal to a processor via a physical interrupt pin of the memory device, so that the processor handles the one or more interrupt events of the memory device according to the interrupt signal.
A method for handling interrupts in a memory device, wherein the memory device comprises a memory cell array and a control logic, and the control logic controls the memory cell array in response to a command from a processor, the method comprising:
- detecting one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array;
- determining whether to assert an interrupt signal according to the detected one or more event parameters;
- and
- when it is determined to assert the interrupt signal, directly sending the interrupt signal to the processor through a physical interrupt pin of the memory device to utilize the processor to handle the one or more interrupt events of the memory device in response to the interrupt signal.
Dependencies are inferred from the claim text.