Methods, systems and apparatus to improve convolution efficiency

A hardware accelerator comprising:

• a hardware data path element (DPE) in a DPE array, the hardware DPE including:
• means for multiplying first inputs, the first inputs including an activation value and a filter coefficient value, the multiplying means to generate a first convolution output when the hardware DPE is in a convolution mode;
• and
• means for accumulating convolution outputs including the first convolution output;
• and
• means for adjusting the hardware DPE from the convolution mode to a pooling mode by causing the hardware DPE to generate a second convolution output based on second inputs, the second inputs including an output location value of a pool area, at least one of the first inputs different from at least one of the second inputs.

A hardware accelerator comprising:

• a data path element (DPE) array including a plurality of hardware DPEs, a first DPE of the plurality of the hardware DPEs including:
• an accumulator;
• and
• a multiplier coupled to the accumulator;
• a connection multiplexer coupled to the DPE array;
• a data store coupled to the connection multiplexer;
• a coefficient store coupled to the DPE array;
• and
• a controller coupled to the DPE array, the coefficient store, and the data store.