Branch prediction based on load-path history

An apparatus comprising:

• a processor configured to execute instructions, wherein the processor comprises at least a load-path history based branch predictor,
• wherein the load-path history based branch predictor comprises:
• a branch identification (ID) table comprising one or more entries, with each entry comprising at least a tag field, and an accuracy counter;
• and
• a prediction counter pool comprising a plurality of prediction counters;
• wherein for a branch instruction fetched by the processor for execution, the branch identification (ID) table is indexed based on a function of a program counter (PC) value of the branch instruction;
• for a tag hit at an entry of the branch ID table indexed by the PC value wherein the tag field of the entry matches the PC value, if a value of the accuracy counter is greater than or equal to zero, a prediction counter is selected from the prediction counter pool,
• wherein each of the plurality of prediction counters in the prediction counter pool comprises at least a respective confidence value and a prediction value,
• wherein the prediction counter is selected based on a function of the PC value and a load-path history,
• wherein the load-path history comprises information from prior load instructions executed by the processor;
• and
• the load-path history based branch predictor is configured to assign a memory-dependent branch prediction of the branch instruction as the prediction value of the selected prediction counter if the confidence value of the selected prediction counter is greater than zero.

An apparatus comprising:

• means for executing instructions;
• means for storing one or more entries for predicting memory-dependent branch instructions, each entry comprising at least means for storing a tag value and means for storing an accuracy value for the entry, wherein for a branch instruction fetched for execution by the means for executing instructions, the means for storing the one or more entries is indexed based on a function of a program counter (PC) value of the branch instruction;
• a plurality of means for indicating prediction values and associated confidence values;
• wherein, for a tag hit at an entry of the branch ID table indexed by the PC value, wherein the tag value matches the PC value, if the accuracy value is greater than or equal to zero, means for selecting one of the plurality of means for indicating, based on a function of the PC value and a load-path history, wherein the load-path history comprises information from prior load instructions executed by the means for executing instructions;
• and
• means for assigning a memory-dependent branch prediction of the branch instruction as the prediction value of the selected means for indicating if the associated confidence value is greater than zero.

A non-transitory computer-readable storage medium comprising code, which, when executed by a computer causes the computer to perform branch prediction in a processor, the non-transitory computer-readable storage medium comprising:

• for a branch instruction fetched by the processor for execution, code for indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein the branch ID table comprises one or more entries, with each entry comprising at least a tag field, and an accuracy counter;
• for a tag hit at an entry of the branch ID table indexed by the PC value, wherein the tag field of the entry matches the PC value, if a value of the accuracy counter is greater than or equal to zero, code for selecting a prediction counter from a prediction counter pool comprising a plurality of prediction counters,
• wherein each of the plurality of prediction counters in the prediction counter pool comprises at least a respective confidence value and a prediction value,
• wherein the code for selecting is based on a function of the PC value and a load-path history,
• wherein the load-path history comprises information from prior load instructions executed by the processor;
• and
• code for assigning a memory-dependent branch prediction of the branch instruction as the prediction value of the selected prediction counter if the confidence value of the selected prediction counter is greater than zero.