Commit logic and precise exceptions in explicit dataflow graph execution architectures
AssigneeMicrosoft Technology Licensing, LLC
InventorsGagan Gupta, David T. Harper
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AssigneeMicrosoft Technology Licensing, LLC
InventorsGagan Gupta, David T. Harper
Estimating the term…
Systems and methods are disclosed for executing instructions with a block-based processor. Instructions can be executed in any order as their dependencies arrive, but the individual instructions are committed in a serial fashion. Further, exception handling can be performed by storing transient state for an instruction block and resuming by restoring the transient state. This allows programmers to see intermediate state for the instruction block before the subject block has committed. In one examples of the disclosed technology, a method of operating a processor executing a block-based instruction set architecture includes executing at least one instruction encoded for an instruction block, responsive to determining that an individual instruction of the instruction block can commit, advancing a commit frontier for the instruction block to include all instructions in the instruction block that can commit, and committing one or more instructions inside the advanced commit frontier.
An apparatus comprising a processor configured to execute a block-based processor instruction set, the apparatus comprising:
A method of operating a processor executing a block-based instruction set architecture, the method comprising:
A method of operating a processor executing a block-based instruction set architecture, the method comprising:
Dependencies are inferred from the claim text.