Using loop exit prediction to accelerate or suppress loop mode of a processor

A method comprising:

• in a processor, in response to predicting a number of loop iterations:
• storing a set of loop instructions in a loop buffer;
• placing a component of an instruction pipeline of the processor in a low-power mode;
• executing the set of loop instructions from the loop buffer;
• predicting a loop exit by a loop exit predictor of the processor;
• and
• restoring power to the component placed in the low-power mode based on the predicted loop exit.

A processor comprising:

• an instruction cache having a set of loop instructions for the processor;
• a loop buffer configured to store the set of loop instructions;
• a loop exit predictor configured to predict a number of loop iterations;
• and
• wherein the processor is configured to:
• in response to the predicted number of loop iterations exceeding a first loop iteration threshold, execute the set of loop instructions in a loop mode, including to:
• place at least one component of an instruction pipeline of the processor in a low-power mode;
• and
• execute the set of loop instructions from the loop buffer;
• and
• in response to the predicted number of loop iterations being less than or equal to the first loop iteration threshold, execute the set of loop instructions in a non-loop mode, including to:
• maintain the at least one component of the instruction pipeline in an active state;
• and
• execute the set of loop instructions fetched from the instruction cache by an instruction fetch unit of the instruction pipeline.