Arithmetic processing device, information processing apparatus, and method for controlling arithmetic processing device
AssigneeFujitsu Limited
InventorMasanori Higeta
Life of this patent
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Abstract
An arithmetic processing device includes: a memory controller that accesses a main storage device; a plurality of arithmetic processing cores that execute instructions; an instruction controller that controls execution of an access instruction to load and store data in the plurality of arithmetic processing cores from and to the main storage device; and a transfer controller that controls data transfer between the memory controller and the plurality of arithmetic processing cores in accordance with an instruction from the instruction controller.
Claims2
An arithmetic processing device comprising:
- a memory controller that accesses a main storage device;
- a plurality of arithmetic processing cores that execute instructions;
- an instruction controller that controls execution of an access instruction to load and store data in the plurality of arithmetic processing cores from and to the main storage device;
- a transfer controller that:
- controls data transfer between the memory controller and the plurality of arithmetic processing cores in accordance with an instruction from the instruction controller;
- and
- divides data read from the main storage device with a single request into first data to be supplied to a first arithmetic processing core of the plurality of arithmetic processing cores and second data to be supplied to a second arithmetic processing core of the plurality of arithmetic processing cores and supplies the first and second data.
An information processing apparatus comprising:
- a main storage device that stores data;
- and
- an arithmetic processing device coupled to the main storage device,
- the arithmetic processing device includes:
- a memory controller that accesses the main storage device;
- a plurality of arithmetic processing cores that execute instructions;
- an instruction controller that controls execution of an access instruction to load and store data in the plurality of arithmetic processing cores from and to the main storage device;
- and
- a transfer controller that:
- controls data transfer between the memory controller and the plurality of arithmetic processing cores in accordance with an instruction from the instruction controller;
- and
- divides data read from the main storage device with a single request into first data to be supplied to a first arithmetic processing core of the plurality of arithmetic processing cores and second data to be supplied to a second arithmetic processing core of the plurality of arithmetic processing cores and supplies the first and second data.
Dependencies are inferred from the claim text.