Data element comparison processors, methods, systems, and instructions

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor to receive a data element comparison instruction, the instruction indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations, the processor, in response to the instruction, to store at least one result mask operand in the one or more destination storage locations, the at least one result mask operand to include a different mask bit for each corresponding data element in one of the first and second source packed data operands in a same relative position, each mask bit to indicate whether the corresponding data element in said one of the first and second source packed data operands equals any of the data elements in the other of the first and second source packed data operands;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing a sparse vector-sparse vector arithmetic algorithm, the sparse vector-sparse vector arithmetic algorithm to include a masked data element consolidation instruction that is to indicate the at least one result mask operand as a source operand to mask a data element consolidation operation.