Hardware Acceleration Method, Compiler, and Device

A hardware acceleration method implemented by a compiler, the hardware acceleration method comprising:

• obtaining source code;
• compiling a first code segment in the source code into first executable code matching a first processor;
• sending the first executable code to the first processor;
• determining, according to first execution information of executing the first executable code, that a second code segment corresponding to the first executable code matches a second processor;
• compiling the second code segment into a second executable code;
• and
• sending the second executable code to the second processor.

A compiler comprising:

• a non-transitory computer readable storage medium configured to store at least one computer-executable instruction;
• and
• a processor coupled to the non-transitory computer readable storage medium and configured to execute the computer-executable instructions to:
• obtain compilation policy information and source code, wherein the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor;
• determine a first code segment belonging to the first code type and a second code segment belonging to the second code type;
• compile the first code segment into first executable code;
• send the first executable code to the first processor;
• compile the second code segment into second executable code;
• and
• send the second executable code to the second processor,
• wherein when a priority of a first process corresponding to the second code segment is higher than a priority of a second process corresponding to a third executable code being executed in the second processor, before sending the second executable code to the second processor, the processor is further configured to execute the computer-executable instructions to:
• stop the third executable code when a busy degree of the second processor is higher than a first preset threshold;
• compile a third code segment corresponding to the third executable code into a fourth executable code matching the first processor;
• and
• send the fourth executable code to the first processor.

A compiler comprising:

• a non-transitory computer readable storage medium configured to store computer-executable instructions;
• and
• a processor coupled to the non-transitory computer readable storage medium and configured to execute the computer-executable instructions to:
• obtain a source code;
• compile, a first code segment in the source code into first executable code matching a first processor;
• send the first executable code to the first processor;
• determine, according to first execution information of executing the first executable code, that a second code segment corresponding to the first executable code matches a second processor;
• compile the second code segment into a second executable code;
• and
• send the second executable code to the second processor.