Memory module and memory system including the same
AssigneeSK hynix Inc.
InventorJong-Ho JUNG
Life of this patent
Estimating the term…
Abstract
A memory module includes a plurality of memory devices; a plurality of data buffers suitable for exchanging data with a memory controller; and a module controller suitable for transferring the data between the memory devices and the data buffers based on a command, an address and a clock provided from the memory controller, calculating delay times for transferring the data according to locations of the data buffers, and controlling times at which the data are transferred based on the calculated delay times.
Claims21
A memory module comprising:
- a plurality of memory devices;
- a plurality of data buffers suitable for exchanging data with a memory controller;
- and
- a module controller suitable for transferring the data between the memory devices and the data buffers based on a command, an address and a clock provided from the memory controller, calculating delay times for transferring the data according to locations of the data buffers, and controlling times at which the data are transferred based on the calculated delay times.
A memory system comprising:
- a memory module;
- and
- a memory controller suitable for providing a command, an address and a clock to the memory module, and exchanging data with the memory module,
- wherein the memory module includes:
- a plurality of memory devices;
- a plurality of data buffers suitable for exchanging data with the memory controller;
- and
- a module controller suitable for transferring the data between the memory devices and the data buffers based on the command, the address and the clock, calculating delay times for transferring the data according to locations of the data buffers, and controlling times at which the data are transferred based on the calculated delay times.
An operating method of a memory module, the operating method comprising:
- generating, in a training mode, a plurality of additional delay signals by counting clock cycles from when a training signal transferred from a data buffer, among multiple data buffers, located farthest from a module controller to when training signals transferred from the other of the multiple data buffers become enabled;
- and
- selectively delaying the data transferred from the data buffers based on the additional delay signals and outputting the delayed data to memory devices, in a write operation.
A memory module comprising:
- a plurality of memory devices suitable for storing data;
- a plurality of buffers suitable for buffering data to be stored in the memory devices;
- and
- a controller suitable for aligning in time buffered data according to delay-compensation times, and providing the aligned data to the memory devices,
- wherein the buffered data are provided from the buffers which are disposed at different locations with reference to the controller, and
- wherein the controller generates the delay-compensation times based on relative delays of training data provided from the buffers to the controller, respectively.
Dependencies are inferred from the claim text.