Methods and systems for using state vector data in a state machine engine

A method, comprising:

• selecting a rank of state machine engines coupled to a common chip select;
• receiving state vector data from a first state machine lattice of a first state machine engine of the rank of state machine engines at an intra-rank (IR) bus and process buffer interface of a second state machine engine of the rank of state machine engines;
• transmitting the state vector data from the IR bus and process buffer interface to an input buffer of a state vector system of the second state machine engine;
• transmitting the state vector data from the input buffer of the state vector system to a second state machine lattice of the second state machine engine, wherein the state vector data includes a state vector as an indication of a state of all or certain configurable elements of the first state machine lattice at a given moment as an indication of a particular state of the first state machine lattice;
• receiving at an output buffer of the state vector system the second state vector data from the second state machine lattice;
• and
• providing the second state vector data from the output buffer to the first state machine lattice via the IR bus and process buffer interface.

A system, comprising:

• a host device comprising a chip select;
• a first state machine engine coupled to the chip select;
• and
• a second state machine engine coupled to the chip select, wherein the first state machine engine comprises:
• a state machine lattice configured to generate state vector data, wherein the state vector data includes a state vector as an indication of a state of all or certain configurable elements of the state machine lattice at a given moment as an indication of a particular state of the state machine lattice;
• a cache configured to store second state vector data;
• a buffer coupled to the state machine lattice and the cache and configured to receive the state vector data from the state machine lattice and the second state vector data from the cache;
• and
• an intra-rank (IR) bus and process buffer interface configured to facilitate the analyzing of multiple data sets in parallel through a logical rank of state machine lattices, wherein the IR bus and process buffer interface is coupled to the buffer, wherein the buffer is configured to provide the state vector data and the second state vector data to the intra-rank (IR) bus and process buffer interface.