US 2020/0089415 A1 · MEMORY SYSTEM CAPABLE OF ACCESSING MEMORY CELL ARRAYS IN PARALLEL

Abstract

According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in the order.

Claims21

Dependent claims

1-20. (canceled)

A memory system comprising:

a controller;
and
a nonvolatile memory chip configured to be controlled by the controller, the nonvolatile memory chip including:
a first memory cell array including a plurality of first memory cells connected to a first word line;
a second memory cell array including a plurality of second memory cells connected to a second word line;
a first decoder configured to select, on the basis of an address received from the controller, the first word line of the first memory cell array;
a second decoder configured to select, on the basis of an address received from the controller, the second word line of the second memory cell array;
and
an access circuit configured to
read, in parallel, first data from the plurality of first memory cells connected to the selected first word line of the first memory cell array and second data from the plurality of second memory cells connected to the selected second word line of the second memory cell array.

7 more elements

A method of controlling a nonvolatile memory chip,

the nonvolatile memory chip including:
a first memory cell array including a plurality of first memory cells connected to a first word line;
a second memory cell array including a plurality of second memory cells connected to a second word line;
a first decoder configured to select, on the basis of an address received from a controller, a first word line of the first memory cell array;
and
a second decoder configured to select, on the basis of an address received from the controller, a second word line of the second memory cell array,
the method comprising:
issuing a first command that includes a first address and a second address to the nonvolatile memory chip to instruct the nonvolatile memory chip to:
select, on the basis of the first address, the first word line of the first memory cell array;
select, on the basis of the second address, the second word line of the second memory cell array;
and
read, in parallel, first data from the plurality of first memory cells connected to the selected first word line of the first memory cell array, and second data from the plurality of second memory cells connected to the selected second word line of the second memory cell array.

9 more elements

A nonvolatile memory chip comprising:

a first memory cell array including a plurality of first memory cells connected to a first word line;
a second memory cell array including a plurality of second memory cells connected to a second word line;
a first decoder configured to select, on the basis of an address received from a controller, the first word line of the first memory cell array;
a second decoder configured to select, on the basis of an address received from the controller, the second word line of the second memory cell array;
and
an access circuit configured to
read, in parallel, first data from the plurality of first memory cells connected to the selected first word line of the first memory cell array and second data from the plurality of second memory cells connected to the selected second word line of the second memory cell array.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/688,411Filed 19 Nov 2019

Priority

10 Mar 2016

Published

19 Mar 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 3/0611
Improving I/O performance: in relation to response time
G06F 3/0656
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: data buffering…
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 3/0679
Single storage device: non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Family

Application62/306,493Us provisional application · filed 10 Mar 2016

Application15/264,119Continuation · filed 13 Sep 2016

Application16/199,803Continuation · filed 26 Nov 2018

Application16/688,411Continuation

US 10,175,889 B2Related patent

US 10,521,129 B2Related patent

US 10,895,990 B2Related patent

US 2017/0262192 A1Published application

US 2019/0095108 A1Published application

US 2020/0089415 A1This patent

From the US filing history. Foreign family members aren’t listed.

Memory system capable of accessing memory cell arrays in parallel

Life of this patent

Memory system capable of accessing memory cell arrays in parallel

Life of this patent

Abstract

Claims21