Drift detection in timing signal forwarded from memory controller to memory device
AssigneeRambus Inc.
InventorsJun Kim, Pak Shing Chau, Wayne S. Richardson
Life of this patent
Estimating the term…
Abstract
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
Claims21
(canceled)
An integrated circuit (IC) memory device comprising:
- a memory core to store data;
- a first interface circuit to receive a first timing signal and a second timing signal from a memory controller, the second timing signal having a frequency which is a fraction of a frequency of the first timing signal, wherein the IC memory device receives data from the memory controller using the first timing signal;
- a delay circuit that mimics a propagation delay of the first timing signal through a clock distribution circuit using the second timing signal to generate a digital code that is representative of a phase of the second timing signal;
- and
- a transmitter to output the digital code to the memory controller.
A method of operating an integrated circuit (IC) memory device including a memory core that stores data, the method comprising:
- receiving a first timing signal and a second timing signal from a memory controller, the second timing signal having a frequency which is a fraction of a frequency of the first timing signal, wherein data is received by the IC memory device from the memory controller using the first timing signal;
- mimicking a propagation delay of the first timing signal through a clock distribution circuit using the second timing signal to generate a digital code that is representative of a phase of the second timing signal;
- and
- outputting the digital code to the memory controller.
An integrated circuit (IC) memory device comprising:
- a means for storing data;
- a means for receiving a first timing signal and a second timing signal from a memory controller, the second timing signal having a frequency which is a fraction of a frequency of the first timing signal, wherein the IC memory device receives data from the memory controller using the first timing signal;
- a means for mimicking a propagation delay of the first timing signal through a clock distribution circuit using the second clock signal to generate a digital code that is representative of a phase of the second timing signal;
- and
- a means for outputting the digital code to the memory controller.
Dependencies are inferred from the claim text.