Phase-locked loop and delay-locked loop

Abstract

Disclosed is a phase-locked loop which alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal. When the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a memory device.

Dependencies are inferred from the claim text.