Minimum-Size Belief Propagation Network for FEC Iterative Encoders and Decoders and Related Routing Method

Interconnection network (110,200) for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages;

• wherein N is a non-prime positive integer, and wherein M is a positive integer equal to, or higher than, two;
• wherein the M stages include a first stage and a last stage and wherein each stage includes switching elements (111,112,113) having, each, respective input pins and respective output pins;
• wherein the input pins of the switching elements (112) of the first stage are connected to the input terminals, and the output pins of the switching elements (113) of the last stage are connected to the output terminals;
• wherein, the input and output pins of the switching elements (111,112,113) of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing, each, respective input values from respective output pins of the switching elements (112) of the first stage to respective input pins of the switching elements (113) of the last stage;
• whereby the interconnection network (110,200) is operable to route, on the basis of routing commands applied to the switching elements (111,112,113), N input values received at the N input terminals through the M stages and the interconnection sub-networks to provide, at the N output terminals, N output values corresponding to, or circularly shifted with respect to, said N input values received at the N input terminals;
• characterized in that M denotes a number of given submultiples of N whose product is equal to N;
• wherein each stage is associated with a respective submultiple of said M given submultiples of N, and includes Si switching elements (111,112,113), each having smi respective input pins and smi respective output pins, wherein Si=N/smi, wherein smi denotes said respective submultiple associated with said stage, and wherein i denotes said stage and is a positive integer comprised between one and M;
• wherein each switching element (111,112,113) is configured to:
• receive, at the smi respective input pins, smi respective input values;
• and
• provide at the smi respective output pins, on the basis of a respective routing command applied to said switching element (111,112,113), smi respective output values corresponding to, or circularly shifted with respect to, said smi respective input values received at the smi respective input pins;
• wherein the interconnection sub-networks are not connected to each other;
• and wherein the interconnection network includes sm1 interconnection sub-networks for routing, each, N/sm1 respective input values from N/sm1 respective output pins of the switching elements (112) of the first stage to N/sm1 respective input pins of the switching elements (113) of the last stage;
• wherein sm1 denotes the submultiple, among said M given submultiples of N, which is associated with the first stage.