US 2020/0074304 A1 · NEURAL NETWORKS FOR EMBEDDED DEVICES

Abstract

A neural network architecture is used that reduces the processing load of implementing the neural network. This network architecture may thus be used for reduced-bit processing devices. The architecture may limit the number of bits used for processing and reduce processing to prevent data overflow at individual calculations of the neural network. To implement this architecture, the number of bits used to represent inputs at levels of the network and the related filter masks may also be modified to ensure the number of bits of the output does not overflow the resulting capacity of the reduced-bit processor. To additionally reduce the load for such a network, the network may implement a “starconv” structure that permits the incorporation of nearby nodes in a layer to balance processing requirements and permit the network to learn from context of other nodes.

Claims20

Dependent claims

A method of generating a neural network structure including one or more input layers each associated with one or more filters, the method comprising:

determining, for an architecture of a device, a bit length of a set of registers of the device used to perform arithmetic operations;
determining a first integer representation for the one or more input layers and a second integer representation for the one or more filters, the first integer representation associated with a first range of integer values and the second integer representation associated with a second range of integer values;
generating dimensionalities of the one or more input layers and the one or more filters, the dimensionalities determined such that an output value generated by combining elements of an input layer as maximum values of the first integer representation with elements of a corresponding filter as maximum values of the second integer representation does not overflow the bit length of the registers;
and
generating the neural network structure with the determined dimensionalities.

2 more elements

A non-transitory computer-readable medium containing instructions for execution on a processor, the instructions comprising:

determining, for an architecture of a device, a bit length of a set of registers of the device used to perform arithmetic operations;
determining a first integer representation for the one or more input layers and a second integer representation for the one or more filters, the first integer representation associated with a first range of integer values and the second integer representation associated with a second range of integer values;
generating dimensionalities of the one or more input layers and the one or more filters, the dimensionalities determined such that an output value generated by combining elements of an input layer as maximum values of the first integer representation with elements of a corresponding filter as maximum values of the second integer representation does not overflow the bit length of the registers;
and
generating the neural network structure with the determined dimensionalities.

2 more elements

A system comprising:

a processor configured to execute instructions;
a computer-readable medium containing instructions for execution on the processor, the instructions causing the processor to perform steps of:
determining, for an architecture of a device, a bit length of a set of registers of the device used to perform arithmetic operations;
determining a first integer representation for the one or more input layers and a second integer representation for the one or more filters, the first integer representation associated with a first range of integer values and the second integer representation associated with a second range of integer values;
generating dimensionalities of the one or more input layers and the one or more filters, the dimensionalities determined such that an output value generated by combining elements of an input layer as maximum values of the first integer representation with elements of a corresponding filter as maximum values of the second integer representation does not overflow the bit length of the registers;
and
generating the neural network structure with the determined dimensionalities.

4 more elements

Dependencies are inferred from the claim text.

Neural networks for embedded devices

Life of this patent

Neural networks for embedded devices

Life of this patent

Abstract

Claims20